基于UVM验证方法学的AES IP验证AES IP Verification Based on UVM
孙铮
摘要(Abstract)：
本文应用UVM(Universal Verification Methodology)高级验证方法学,搭建适用于AES(Advanced Encryption Standard)高级加密算法IP的验证平台和验证环境,并实现对其加密过程和解密过程的功能验证,提供了一种可重用的高效验证方法,有利于提高验证效率,缩短设计周期。
关键词(KeyWords)： UVM;验证方法学;AES
基金项目(Foundation):
作者(Author): 孙铮
DOI: 10.16453/j.issn.2095-8595.2014.01.007
参考文献(References)：
- [1]李磊,罗胜钦.基于VMM方法的SOC集成验证[J].电子测量技术,2011.
- [2]C.Lu,S.Tseng.Integrated Design of AES(Advanced Encryption Standard)Encrypter andDecrypter,Proceedings of the IEEE International Conference on Application-Specific Systems,Architectures,and Processors(ASAP'02),IEEE,2002.
- [3]Accdlera.Universal verification methodology 1.1 user's guide[M].Cadence Design Systems Inc.,Mentor Graphics Corp.,Synopsys Inc.,2011.
- [4]Chris Spear.System Verilog for verification[M].Synopsys Inc.,2008Acdlera.Universal verification methodology1.1clas reference[M].
- [5]Cadence Design Systems Inc.,MentorGraphics Corp.,Synopsys Inc.,2011.